Be a Changemaker in the World of Semiconductors

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

• Responsible to bridges high-tech industry demands with workforce training, talent pipeline development, and institutional operations. The GM leads the strategy, curriculum alignment, industry partnerships, and revenue/operational management of a specialized semiconductor training hub or center of excellence.
• Responsible to lead the overall strategic direction, daily operations, academic/industry program delivery, and stakeholder ecosystem of the SMD Academy. The primary focus is building a sustainable, high-impact talent development engine that aligns with local and global semiconductor ecosystem needs.

Job Responsibilities

•  Formulate and execute multi-year strategic roadmaps aligned with National Semiconductor Strategy & Sarawak Semiconductor Roadmap 2030 to establish the Academy as a top-tier chip design and microelectronics talent hub.
• Serve as the primary liaison to key government bodies, state investment arms, and multinational semiconductor corporations to align talent outcomes with regional economic transformation goals.
• Drive revenue generation through industry-sponsored training programs, corporate talent upskilling, government grants, and certification courses.
• Direct and elevate the academy’s current flagship initiatives to the next level—specifically the Mastery Program, the IC Design Competition, and the Make-a-thon—scaling their industry impact, participant reach, and technical rigor.
• Oversee outreach and recruitment efforts to attract top engineering talent, university graduates, TVET candidates, and mid-career professionals into chip design, tape-out, verification, and hardware development paths.
• Collaborate with technical advisory boards and industry partners to ensure all training modules meet current and emerging industry needs.
• Oversee the end-to-end development of certification programs, hands-on lab training, and university-to-industry bridging courses.
• Ensure training labs are equipped with industry-standard software, simulation tools, and hardware setups.
• Lead daily operations, facility management, and administrative functions of the academy campus and laboratories.
• Own and manage the annual budget preparation, capital expenditure for lab equipment/EDA licensing, and financial forecasting.
• Drive outreach, recruitment campaigns, and scholarship initiatives to attract engineering talent, graduates, and mid-career upskillers.

Job Requirements

• Bachelor’s or Master’s degree in Electrical/Electronic Engineering, Microelectronics, Physics, Business Administration, or a related field.
• Ph.D. in Microelectronics, VLSI, IC Design, or related STEM fields is a distinct advantage. An MBA or senior management certification is highly desirable.
• Minimum 12–15 years of combined experience across the semiconductor/electronics sector and technical workforce education/training management.
• Minimum 5 years in a managerial capacity overseeing P&L, multi-disciplinary engineering teams, or enterprise workforce training programs.
• Deep understanding of the semiconductor value chain and industry talent gaps.
• Familiarity with modern chip design flows (RTL-to-GDSII, Analog Mixed-Signal, Verification methodologies), embedded systems, and advanced packaging trends, is an added advantage.
• Demonstrated track record in grant writing, business development, corporate training commercialization, and CapEx/OpEx financial stewardship.
• Exceptional communication skills with a proven track record negotiating with government ministers, MNC executives, university leaders, and global EDA vendors.

Career Level

Senior Manager

Years of Experience

12-15 years

Qualification

Job Type

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

Job Responsibilities

• Lead full lifecycle delivery of utility-scale solar PV and BESS projects from Notice to Proceed through construction, grid synchronization, commissioning, and final Commercial Operation Date, ensuring strict scope, schedule, cost, quality, and safety parameters.
• Direct multi-disciplinary EPCC contractors, OEMs, engineering consultants, and subcontractors, managing resource deployment strategies, integrated master schedules, capital budgets, and quantitative risk registers.
• Oversee high-voltage infrastructure (up to 275kV substations and transmission lines), ensuring strict compliance with applicable regional grid codes and managing interface risks across civil, electrical, and BESS components.
• Provide technical leadership to review PV design optimization, energy yield assessments (e.g., PVsyst), and BESS sizing/control parameters to maximize performance ratio (PR) and optimize LCOE.
• Drive technical specifications, supplier qualification, design approvals, and Factory Acceptance Testing (FAT) for long-lead Tier-1 PV modules, inverters, BESS containers, and HV switchgear.
• Oversee design integration of SCADA, Energy Management Systems (EMS), and industrial communication protocols for real-time telemetry, grid dispatch, and remote control.
• Act as the primary technical interface between senior leadership, asset owners, EPCC partners, equipment suppliers, and international technology partners in governance forums.
• Navigate regulatory bodies to secure required licenses, land approvals, and permits, ensuring alignment with national and regional renewable energy transition policies.
• Facilitate strategic collaboration with international technology partners to support knowledge transfer and technology integration within the local supply chain.
• Manage capital expenditure for multi-hundred-million-ringgit utility-scale developments, exercising cost control, Earned Value Management (EVM), and cash flow forecasting.
•  Oversee procurement execution and administration of EPC/EPCC contracts and supply agreements, managing variation orders, EOT claims, progress payments, and commercial close-outs.
• Champion a proactive site safety culture, enforcing full compliance with national occupational health and safety (OHS) regulations, construction industry standards, and international safety benchmarks.
• Implement QA/QC protocols from engineering through Site Acceptance Testing (SAT), enforcing Environmental Management Plans (EMP) and social impact frameworks across ground-mounted, floating, or specialized solar applications.
• Prepare and present progress reports to executive leadership and external stakeholders, tracking schedule adherence, budget variance, technical milestones, and safety metrics.
• Lead HV energization, inspection, Reliability Run Tests (RRT), and IOD-to-COD transitions, ensuring seamless handover to operational teams.

Job Requirements

• Bachelor’s Degree in Electrical Engineering, Renewable Energy, Civil Engineering, or a related technical discipline. A Master’s degree is highly advantageous.
• Minimum 10–15 years of progressive experience in project management or construction management within the renewable energy or large-scale infrastructure sector.
• Proven track record of successfully delivering utility-scale solar PV projects of 50MW or larger, from development phase through to commercial operation.
• Deep expertise in utility-scale solar PV system design, performance modelling, yield optimisation, and technology selection is desired.
• Proven experience with battery energy storage systems, including sizing methodologies, control architectures, and grid integration is a plus.
• Comprehensive knowledge of 33kV, 132kV, and 275kV transmission infrastructure, substation design, and grid interconnection protocols.
• Extensive experience in EPCC project workflows, contract management, and construction sequencing for large-scale infrastructure assets.
• Project Management Professional (PMP) or Certified Associate in Project Management (CAPM) from PMI is highly desired.

Career Level

Senior Manager

Years of Experience

10-15 years

Qualification

Bachelor's Degree

Job Type

Full-Time

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

Job Responsibilities

• Develop and implement IT strategies, policies, and procedures that align with the company’s business objectives and growth plans.
• Manage and maintain the company's IT infrastructure, including servers, storage solutions, laptops, CCTVs, printers, monitors, computer peripherals, networks, and cloud-based systems.
• Oversee the procurement and installation of hardware and software.
• Ensure optimal performance and scalability of IT systems.
• Evaluate and implement new EDA CAD tools and technologies to improve the overall design process.
• Ensure EDA design tools are optimized and maintained for smooth and efficient operation.
• Work closely with design teams to develop and implement design flows, design methodologies and best practices.
• Troubleshoot and resolve EDA CAD tool issues.
• Develop and maintain scripts and utilities to automate CAD design processes.
• Stay up-to-date with the latest CAD tools and technologies, and implement them where appropriate.
• Lead and mentor a small IT team, providing guidance and support.
• Coordinate and delegate tasks to team members, setting clear expectations.
• Foster a collaborative and productive work environment.
• Develop and implement robust cybersecurity measures to protect company data and systems.
• Monitor and respond to security incidents and vulnerabilities.
• Stay up-to-date with industry best practices and emerging threats.
• Collaborate with external vendors and service providers to optimize IT services.
• Negotiate contracts and agreements to ensure cost-effectiveness and quality.
• Provide hands-on technical support to end-users, troubleshooting hardware and software issues.
• Develop and maintain an IT helpdesk system for issue tracking and resolution.
• Evaluate and recommend IT solutions that align with business objectives.
• Develop and manage the IT budget.
• Maintain accurate records of IT assets, configurations, and procedures.
• Ensure compliance with relevant data protection and regulatory requirements.
• Develop and implement a comprehensive ISO 27001:2013 Information Security Management System (ISMS) certification strategy and roadmap for the organization.

Job Requirements

• Bachelor’s Degree in Computer Science, Information Technology, Engineering, or a related field.
• Preferred at least 10 years of progressive experience in IT roles, with at least 2 years in an IT management or leadership capacity.
• Proven experience in managing IT environment for high-tech engineering company, or EDA tools is an added advantage.
• Understanding of EDA tools licensing mechanisms and requirements is an added advantage.
• Knowledge of information security best practice, risk management, and data privacy principles.
• Solid understanding of networking concepts and network security.
• Proficiency in windows server administration, active directory and Microsoft 365.
• Experience with cloud platforms and strong knowledge of scripting.
• Experience with backup and disaster recovery solutions.
• Strong communication, interpersonal, and leadership skills with the ability to effectively communicate technical information to non-technical stakeholders.
• Ability to work independently, prioritize tasks, and manage multiple projects simultaneously in a dynamic environment.

Career Level

Manager

Years of Experience

10 years

Qualification

Bachelor's Degree

Job Type

Full-Time

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

The Staff Analog IC Design Engineer will be responsible for designing, developing and verifying analog IPs using CMOS / BCD / HV technology. In addition to the design work, he/she will be involved in the supervision of layout work, and customer support on IP design services.

Job Responsibilities

• Work with business teams and system level engineers to define mutually agreeable specifications on the system level.
• Providing high-level analysis of chip architecture tradeoffs, Analog and IO placements, Digital/SRAM block placements, and selection of the right memory to ensure the best solution for a given product based on the specifications given.
• Responsible to design and integrate the analog building blocks into bigger systems for example: POR, ADC, DAC, LDO, PLL, Temperature Sensors, DC-DC converters using industry EDA tools (Cadence, Mentor, or Synopsys).
• Supervise IC layouts to achieve the optimal design performance vs area.
• Write Verilog-A behavioral models for quick simulation, prototyping and analysis.
• Support the Mixed Signal Design Engineer with top level simulations to ensure the correct integration of analog, digital and software components.
• Participate in design reviews and create the necessary design and product documentation.
• Work together with the Product Verification Engineers to perform lab evaluation and validation of complex ICs.
• Collaborate with Test Solution Development Engineers to ensure the design to be fully and efficiently tested.
• Support Root Cause and Failure Analysis investigations.
• Stay up to date with the latest trends and developments in the semiconductor industry and leverage that knowledge to improve the design process and product offerings.
• Work with multi-disciplinary and international project team members.
• Responsible to develop and mentor junior engineers.

Job Requirements

• Engineering degree in Electronics, Physics or other related fields.
• Knowledge of CMOS process and devices parasitics.
• Minimum 8 years of experience designing analog block design such as bandgap references, LDO regulators, amplifiers, comparators, VCOs.
• Experience with various analog circuit design techniques, such as noise analysis, stability analysis, and feedback analysis.
• Hands-on experience with EDA tools such as Cadence, Synopsys, Siemens.
• Knowledge of Verilog A/AMS modeling is considered a plus.
• Understanding of simulation models, design rules and verification procedures (DRC/LVS/ERC).
• Familiar with 6-sigma design practices and good understanding of statistical analysis.
• Excellent written and oral communications skills.
• Able to work independently on complex technical and/or engineering tasks.
• Flexible to respond to dynamic work and customer needs.
• Team player, passionate about technology, solution driven.
• Self-motivated and able to take full responsibility for solutions.
• Proven skills in project management and project lead.
• Travel may be required for design reviews and collaboration with global teams.

Career Level

Manager

Years of Experience

8 years

Qualification

Job Type

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

We are seeking an experienced Custom Layout Engineer to join our dynamic team. The successful candidate will be responsible for the design and layout of high-performance analog and mixed-signal circuits.

Job Responsibilities

• Work closely with circuit designers to understand circuit specifications and constraints, and develop layout plans accordingly.
• Perform top-level and block-level layout design and verification of complex analog and mixed-signal circuits, including but not limited to amplifiers, ADCs, DACs, bandgap references, LDO regulators, comparators, VCOs, high power drivers and PLLs.
• Conduct layout design optimization and design rule checking to ensure high-quality layouts that meet performance, power, and area requirements.
• Collaborate with CAD engineers and designers to develop and implement layout design methodologies, automation flows, and tool scripts.
• Provide technical guidance and mentorship to junior layout designers, and participate in peer reviews to ensure high-quality designs.
• Participate in design reviews and create the necessary report and design documentation.
• Work with multi-disciplinary and international project team members.

Job Requirements

• Bachelor's or Master's degree in Electrical & Electronics Engineering or related field.
• Minimum 3 years of experience designing analog layout block design such as bandgap references, LDO regulators, amplifiers, comparators, VCOs.
• Minimum 5 years of experience in analog and mixed-signal layout design, with a proven track record of successful tapeouts in advanced technology nodes.
• Proficiency in industry-standard layout tools, such as Cadence Virtuoso, PVS, Mentor Graphics Calibre and Synopsys Custom Compiler, IC Validator.
• Familiarity with scripting languages, such as Skill, Python, Tcl, and Perl.
• Knowledge of CMOS process and devices parasitics.
• Experience with various analog layout design techniques such as matching, symmetry, shielding, and floor planning.
• Excellent written and oral communications skills.
• Able to work independently on complex technical and/or engineering tasks.
• Flexible to respond to dynamic work and customer needs.
• Team player, passionate about technology, solution driven.
• Self-motivated and able to take full responsibility for solutions.
• Travel may be required for design reviews and collaboration with global teams.

Career Level

Senior Executive / Manager

Years of Experience

5 years

Qualification

Bachelor's Degree, Post Graduate Diploma, Master's Degree

Job Type

Full-Time

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

The Senior Analog IC Design Engineer will be responsible to perform independent design of IPs using CMOS / BCD / HV technology. In addition to the design work, he/she will be involved in the supervision of layout work, and customer support on IP design services.

Job Responsibilities

• Responsible to design and integrate the analog building blocks into bigger systems for example: POR, ADC, DAC, LDO, PLL, Temperature Sensors, DC-DC converters.
• Use industry EDA tools (Cadence, Mentor, or Synopsys) for schematic capture and simulation setup to analyze and perform pre and post-layout simulations of the analog basic building blocks across PVT.
• Supervise IC layouts to achieve the optimal design performance vs area.
• Able to write Verilog-A behavioral models for quick simulation and prototyping and analysis.
• Support the Mixed Signal Design Engineer with top level simulations to ensure the correct integration of analog, digital and software components.
• Work together with the Product Verification Engineers to perform lab evaluation and validation of complex ICs.
• Collaborate with Test Engineers to ensure that the design can be efficiently and fully tested in production.
• Participate in design reviews and create the necessary design and product documentation.
• Support Root Cause and Failure Analysis investigations.
• Work with multi-disciplinary and international project team members.
  

Job Requirements

• Engineering degree in Electronics, Physics or other related fields.
• Knowledge of CMOS process and devices parasitics.
• More than 5 years of experience designing analog block design such as bandgap references, LDO regulators, amplifiers, comparators, VCOs.
• Experience with various analog circuit design techniques, such as noise analysis, stability analysis, and feedback analysis.
• Hands-on experience with EDA tools such as Cadence, Synopsys, Siemens.
• Knowledge of Verilog A/AMS modeling is considered a plus.
• Understanding of simulation models, design rules and verification procedures (DRC/LVS/ERC).
• Familiar with 6-sigma design practices and good understanding of statistical analysis.
• Excellent written and oral communications skills.
• Able to work independently on complex technical and/or engineering tasks.
• Flexible to respond to dynamic work and customer needs.
• Team player, passionate about technology, solution driven.
• Self-motivated and able to take full responsibility for solutions.
• Travel may be required for design reviews and collaboration with global teams.

Career Level

Senior Executive 

Years of Experience

5 years

Qualification

Bachelor's Degree, Professional Degree, Master's Degree

Job Type

Full-Time

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

Responsible to guarantee the functional correctness and high quality of complex digital IC designs (written in RTL) before they are committed to silicon. This position offers the opportunity to work on advanced digital designs, focusing on verifying RTL designs for complex systems. While a strong background in RTL verification is essential, familiarity with microcontroller SoC architectures, including RISC-V or ARM, is a plus.

Responsibilities

• Develop and implement testbenches for RTL designs using industry-standard verification methodologies (e.g., UVM, SystemVerilog).
• Collaborate with RTL design engineers to understand design specifications and create comprehensive verification plans.
• Perform RTL simulations and debug design issues, working to ensure the correctness and functionality of the design.
• Develop and execute functional coverage models, identifying potential gaps in verification and ensuring full verification of the RTL.
• Collaborate with cross-functional teams to troubleshoot and resolve design or verification issues.
• Analyze simulation results and work with the design team to resolve failing test cases and identify root causes.
• Assist in the integration of microcontroller SoC components, including CPU cores, memory interfaces, and peripherals (basic knowledge of SoC design such as RISC-V or ARM is an advantage).
• Stay current with industry trends and verification methodologies, particularly those related to microcontroller SoC and processor designs.

Requirements

• Bachelor’s or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
• Minimum of 5 years of experience in verification of RTL designs using SystemVerilog/Verilog and UVM.
• Strong understanding of digital design principles, including timing, functionality, and logic verification.
• Experience with simulation tools (e.g., ModelSim, VCS, Questa) and waveform analysis.
• Familiarity with microcontroller or SoC design concepts (e.g., RISC-V, ARM) is a plus but not required.
• Strong debugging and problem-solving skills.
• Good knowledge of verification planning, including coverage-driven verification techniques.
• Excellent written and verbal communication skills, with the ability to work effectively in a team environment.
• Experience with scripting languages (e.g., Python, Perl, TCL) is a plus.
• Hands-on experience with SoC or microcontroller verification, including peripheral interfaces, memory subsystems, and CPU cores.
• Familiarity with ARM or RISC-V processor cores and their associated instruction sets.
• Knowledge of hardware/software co-verification or embedded systems.
• Experience in automation of testbenches and regression suites.

Career Level

Senior Executive 

Years of Experience

5 years

Qualification

Bachelor's Degree, Master's Degree

Job Type

Full-Time

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

Responsible for the micro-architectural design, RTL implementation, verification, and synthesis of complex digital circuits. You will have the opportunity to contribute to cutting-edge projects and work alongside a team of talented engineers in a collaborative and innovative environment. The ideal candidate should have strong experience in RTL design, using languages such as Verilog/System Verilog/VHDL, with a fundamental understanding of microcontroller SoC architectures, including RISC-V or ARM.

Responsibilities

• Develop RTL code in Verilog or VHDL for digital circuits, including but not limited to CPU cores, memory controllers, and peripheral interfaces.
• Collaborate closely with architects to translate architectural specifications into efficient and high-performance RTL code.
• Integrate various components of a digital system, ensuring compatibility and performance optimization.
• Collaborate with cross-functional teams (software, verification, hardware) to ensure successful product delivery.
• Assist in the design, synthesis, and timing analysis of digital systems.
• Contribute to the development of block-level and chip-level design documentation.
• Perform simulation, debugging, and performance analysis of RTL designs to ensure correctness and efficiency.
• Support RTL design verification activities, working with the verification team to create testbenches and validate designs.
• Stay updated with emerging microcontroller SoC trends and architectures, including knowledge of RISC-V and ARM designs.

Requirements

• Bachelor’s or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or related fields.
• Minimum of 5 years of experience in RTL design and implementation using SystemVerilog Verilog/VHDL.
• Strong understanding of digital design principles, including timing analysis, logic design, and synthesis.
• Familiarity with design tools (e.g., Synopsys, Cadence, Xilinx) for synthesis, simulation, and debugging).
• Basic knowledge of microcontroller or SoC architectures (e.g., RISC-V, ARM) is a plus.
• Excellent problem-solving, debugging and analytical skills.
• Strong communication skills and ability to work collaboratively in a team environment.
• Familiarity with FPGA or ASIC design flows is a plus.
• Hands-on experience with SoC or microcontroller design, including integration of peripherals and memory subsystems.
• Knowledge of ARM/RISC-V vector extensions, custom extensions, or the ARM/RISC-V Privileged Architecture
• Familiarity with ARM or RISC-V instruction set architecture (ISA) and microarchitecture.
• Understanding of ARM-based hardware security (e.g., TrustZone, Secure Boot).
• Familiarity with functional safety standards and practices (e.g., ISO 26262, IEC 61508).
• Experience with embedded systems or low-level programming for microcontrollers.
• Exposure to hardware/software co-design.

Career Level

Senior Executive 

Years of Experience

5 years

Qualification

Bachelor's Degree, Master's Degree

Job Type

Full-Time

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

Responsible for the design, development, and testing of advanced power electronic converters and systems. Also, responsible for driving technical solutions from concept to production, collaborating with cross-functional teams, and mentoring junior engineers.

Responsibilities

Requirements

Career Level

Senior Executive 

Years of Experience

7 years

Qualification

Bachelor's Degree

Job Type

Full-Time

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

Leads design, development and characterization of advanced IC packaging & SiP for silicon and compound power semis, aimed on GaN devices and gate driver ICs.

Job Responsibilities

• Lead the definition and implementation of IC package and System-in-Package (SiP) architectures, including lead frame-based packages (QFN, DFN, LGA), power and high-current packages, and SiP solutions integrating power devices, gate drivers, passives, and control ICs.
  
• Drive package and SiP level trade-offs, balancing electrical performance (parasitics, switching behavior, EMI), thermal performance, heat dissipation, mechanical robustness, and manufacturability.
  
• Lead SiP co-design activities, including die placement, interconnect strategy, substrate and routing considerations, passive integration, and power loop optimization.
  
• Evaluate die-to-die and die-to-package interactions, including electrical coupling, thermal coupling, and stress effects.
  
• Drive SiP platform scalability across product variants and applications, and utilize wafer-level electrical data to inform package and SiP design decisions.
  
• Lead package-level and SiP-level characterization, including electrical parasitic extraction and impact analysis, thermal resistance and transient thermal response, and mechanical stress and warpage effects.
  
• Establish and maintain wafer-to-package-to-SiP correlation models to accelerate learning cycles and reduce design risk.
  
• Define and execute package and SiP characterization plans covering static and dynamic electrical behavior, thermal and power cycling, and assembly- and integration-induced performance shifts.
  
• Contribute to package and SiP reliability strategies with an understanding of JEDEC/AEC qualification concepts and package/interconnect-related failure mechanisms.
  
• Support power stage and gate driver co-packaging to optimize performance and robustness while leading first-build execution, risk mitigation, and failure analysis for packaging and integration issues.
  
• Drive corrective actions with OSATs, substrate suppliers, and internal stakeholders.
  
• Collaborate with internal design and test teams and external partners to enable package-aware silicon design and ensure accurate characterization of SiP effects.
  
• Provide technical leadership in package and SiP readiness reviews across product lifecycle phases (R&D, MPW, pilot, HVM).
  
• Document package and SiP architectures, characterization results, and technical learnings clearly and rigorously, and develop and maintain internal packaging and SiP design guidelines.
  
• Mentor junior engineers and contribute to long-term capability building in IC packaging and integration.

Job Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related discipline.
  
• Minimum 8 years of experience in IC packaging and/or SiP development, and Power Semiconductor or mixed signal IC products.
  
• Strong understanding of IC Packaging & SiP fundamentals, including electrical, thermal, & mechanical interactions, package & substrate parasitics, and high-speed and high-power integration challenges.
  
• Hands-on experience with package and SiP level electrical and thermal characterization, interaction with OSATs and assembly process flows.
  
• Familiarity with GaN or power semiconductor packaging and co-packaging challenges is highly desirable.
  
• Exposure to reliability, qualification testing, or failure analysis methodologies is an advantage.
  
• Detail-oriented with high standards for measurement accuracy and documentation quality.

Career Level

Manager

Years of Experience

8 years

Qualification

Job Type

Job Highlights

• We offer a competitive salary and benefits package.
• Opportunities for professional growth and development.

Job Summary

Responsibile for leading wafer-level and package-level electrical testing and characterization of high voltage GaN HEMT devices and associated game driver.

Job Responsibilities

• Lead comprehensive wafer-level and package-level characterization of 650V GaN HEMT devices, including DC characteristics (I-V, leakage, threshold voltage, and breakdown behavior), dynamic and switching performance, on-resistance, gate charge, and parasitic effects.
  
• Perform electrical characterization of GaN gate driver ICs at both the wafer level (parametric and structural validation) and package level (functional, performance, and stress testing).
  
• Develop, execute, and optimize wafer-level test (WLT) methodologies for process verification, device parametric distributions, and early yield and variability analysis.
  Support package-level test (PLT), including electrical performance validation, package parasitic and thermal impact assessment, and correlation between wafer-level and packaged device results.
  
• Drive WLT-to-PLT correlation and silicon learning loops.
  
• Design and execute test plans for gate driver ICs, including characterization of propagation delay and timing accuracy, output drive strength and switching behavior, common-mode transient immunity (CMTI), and under-voltage lockout (UVLO).
  
• Evaluate driver-to-power-device interaction under dynamic conditions.
  
• Design and maintain custom test hardware, including probe cards, evaluation and demo boards, characterization fixtures, and load boards.
  
• Develop and maintain automated test and data analysis solutions using Python, LabVIEW, MATLAB, or equivalent tools.
  
• Improve test repeatability, throughput, and data integrity through systematic automation and standardization.
  
• Analyze characterization data to identify performance limits, variability drivers, and anomalies; understand process, layout, and packaging sensitivities.
  
• Lead root-cause analysis of electrical failures or unexpected behaviors at both wafer and package levels.
  
• Provide clear, actionable feedback to device and IC designers, packaging and process integration teams, and program development stakeholders.
  
• Work closely with device and analog IC design teams, advanced packaging, program development and project management teams, and applications and product engineering.
  
• Produce clear and thorough documentation of test methods and setups, characterization results and interpretations, and correlation and learning reports.
  
• Support technical reviews and mentor junior engineers in device and IC characterization best practices.

Job Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related discipline.
  
• Minimum 8 years of experience in related fields power semiconductor device characterization, and analog or mixed-signal IC testing, preferably for power applications.
  
• Strong fundamentals in power semiconductor devices, with emphasis on GaN HEMT, physics & behavior, and high-voltage with high-speed switching characteristics.
  
• Hands-on experience with wafer probe systems & parametric testers, advanced bench instrumentation (oscilloscopes, SMUs, power analyzers, AWGs).
  
• Proficiency in test automation and data analysis using Python, LabVIEW, MATLAB or C/C++.
  
• Strong grasp of analog and mixed-signal circuits and their testing considerations, complemented by robust analytical and debugging skills rooted in a methodical, data-driven mindset.
  
• Detail-oriented with high standards for measurement accuracy and documentation quality.

Career Level

Manager

Years of Experience

8 years

Qualification

Bachelor's Degree, Master's Degree

Job Type

Full-Time